Non-volatile (NV) random access memory (RAM) is expected to replace conventional dynamic random access memory (DRAM) in many applications. NV RAM may make use of spin, magnetic, and other forms of phase or structure changing memory cells.
One problem faced by NV RAM is cell failure caused by finite endurance. The physical stress of changing the phase or structure of a memory cell over repeated programming operations may over time reduce the sensed voltage or current levels when performing a read operation, which may result in a read error. The distribution of endurance for an ensemble of memory cells may be represented by a normal distribution, where some of memory cells in the ensemble may fail much earlier than others.
An error correcting code (ECC) circuit may be used in conjunction with NV RAM, but for cost reasons such codes are usually designed to guarantee a corrected error rate based on the assumption that raw (uncorrected) bit errors are random events occurring as memory cells begin to wear out. Accordingly, once a particular memory cell has reached its endurance limit and begins to fail, that cell will burden the error correcting capabilities of an ECC circuit with its consistent failures. This phenomenon is known as an accumulated error, and is no longer modeled as a random event.
One solution is to design the ECC circuit to correct accumulated errors, but this may not be desirable because more parity check bits are required. Another solution would be to simply mark failing cells in an NV RAM so that they are not to be used. Such an approach is used in NAND flash memory. However, this approach will create holes wherever there is a bad cell, and due to the speed at which RAM operates, and also the requirement for RAM memory to be physically contiguous, this approach is suitable only for relatively slow memories that are not random access in nature.